YADRO ASIC+RTL+FPGA MEETUP

--- This website is dedicated to the YADRO ASIC+RTL+FPGA Meetup event, which will take place on March 2, 2024, both in Minsk and online. The event is aimed at engineers working on FPGA-, ASIC- and RTL-design projects, who will have the opportunity to learn from leading engineers and team leaders at YADRO. Topics to be covered include system development and functional verification on silicon, iterative design implementation on FPGA, and approaches to testing and system booking. The program will include six presentations and a discussion on the role of functional verification in the context of total restrictions, led by FPGA-Systems community leader, Mikhail Korobkov. The event is open to those interested in the design of systems on chips, with a focus on practical tools and methodologies used in the field. Registration for both