YADRO ASIC+RTL+FPGA MEETUP

--- The web project "YADRO ASIC+RTL+FPGA MEETUP" is an event for FPGA-, ASIC- and RTL-engineers. It will take place in-person in Minsk and online on March 2, 2024, from 11:00 AM. The program includes six presentations on topics such as system development, functional verification, and iterative assembly of projects on FPGA, ASIC, and RTL. Speakers include leading engineers and team leaders from YADRO, who will share their experiences in designing systems on chips. The agenda covers system design and functional verification cycles, practical tools, and approaches for chip development. Registrations for offline and online attendance have closed, and those interested can subscribe to YADRO's news for updates on future meetups and other events.